1. Field of the Invention
The present invention relates to a delay circuit, and more particularly a delay circuit for digital signal processing which can secure a longer delay time.
2. Description of the Related Art
FIG. 5 shows an example of a conventional delay circuit. The delay circuit shown in FIG. 5 includes: a first inverter constituted by a first P-channel MOS transistor 5-1 and a first N-channel MOS transistor 5-2; a delay section constituted by a resistor 5-7 and a capacitor 5-8; a second inverter constituted by a second P-channel MOS transistor 5-3 and a second N-channel MOS transistor 5-4; and a third inverter constituted by a third P-channel MOS transistor 5-5 and a third N-channel MOS transistor 5-6.
An operation of the delay circuit shown in FIG. 5 will now be described with reference to FIGS. 6A through 6E. FIGS. 6A through 6E are waveforms showing changes of potentials at nodes NA through NE in the delay circuit.
A potential at the node NA is 0 [V] in the initial state (t=t0). If the capacitor 5-8 is assumed not to be charged, the potentials at the nodes NA through NE will be 0 [V], VDD [V], 0 [V], VDD [V], and 0 [V], respectively at t=t0.
In this state, a current flows from the node NB to the node NC through the resistor 5-7 to charge the capacitor 5-8. For this reason, the potential at the node NC is changed in accordance with the following equation. EQU eC=eB(1-exp(t/CR))
wherein eC represents a potential at the node NC; eB, a potential at the node NB; t, an elapsed time, C, a capacitance of the capacitor 5-8, and R, a resistance of the resistor 5-7.
When the potential at the node NC exceeds a threshold value of the second inverter at t=t1, the potential at the node ND drops to 0 [V].
This potential change is inverted by the third inverter. Accordingly, the potential at the node NE raises to VDD [V]. When a time has elapsed sufficiently longer than a time constant determined by the resistance of the resistor 5-7 and the capacitance of the capacitor 5-8, the capacitor 5-8 is charged and the potential at the node NC becomes VDD [V].
If the potential at the node NA (a potential of an input signal) is assumed to be changed to VDD [V] at t=t2, the potential at the node NB becomes 0 [V], so that the capacitor 5-8 discharges through the resistor 5-7 and the N-channel MOS transistor 5-2.
When the potential at the node NC becomes smaller than the threshold value of the second inverter at t=t3, the potential at the node ND raises up to VDD [V]. Then, the potential at the node NE drops to 0 [V].
From a view point of the comparison of the potential change at the node NA with the potential change at the node NE, a voltage (a signal) at the node NE is a signal in which a signal at the node NA is delayed by the time of t1-t0=t3-t2. More specifically, a digital signal input to the node NA is delayed by (t1-t0) and output to the node NE.
FIG. 7 is a circuit diagram showing a delay circuit of Miller integrator type showing another example of a conventional delay circuit. The delay circuit shown in FIG. 7 comprises a first inverter 7-1, a second inverter 7-2, a third inverter 7-3, a fourth inverter 7-4, and a capacitor 7-5.
An operation of the delay circuit shown in FIG. 7 will now be described with reference to FIGS. 8A through 8E. FIGS. 8A through 8E are waveforms showing changes of potentials at the nodes MA through ME in the delay circuit in FIG. 7.
Assume now that the resistance of the resistor 7-4 and the capacitance of the capacitor 7-5 are represented by R [.OMEGA.] and C[F], respectively.
Further, assume that an amplification degree M of the inverter 7-2 is fully large and the potentials at the nodes MA and MD are 0 [V] and VDD [V], respectively in the initial state (t=t0). In this state, the potentials at the nodes MA through ME will be 0 [V], VDD [V], VDD/2 [V], VDD [V], and 0 [V], respectively.
From this state, a current flows from the node MB to the node MC through the resistor 7-4 as the time elapses, and the potential at the node MC raises by .DELTA.1 [V]. This change is amplified by the second inverter 7-2 and thus the potential at the node MD lowers by .DELTA.2 [V].
However, since the capacitor 7-5 is connected between the nodes MC and MD, an output of the second inverter 7-2 is fed back to the input thereof through the capacitor 7-5. This feedback cancels the potential change .DELTA.1 [V] at the node MC so that the potential at the node MC is constantly approximately at VDD/2 [V].
The potential at the node MD is an integrated value of the inverted signal at the node MB and thus has a triangular waveform as shown in FIG. 8D. In this case, the inverter 7-2 linearly amplifies the input signal so that it operates in an active region.
The third inverter 7-3 compares a threshold level (indicated by a broken line in FIG. 8D) with a potential at the node MD and outputs a signal shown in FIG. 8E at the node ME. The potential at the node ME is a signal delayed by a predetermined period of time with respect to the input signal.
According to the conventional delay circuit shown in FIG. 5, a delay time is obtained by comparing a voltage of an output signal of a passive circuit constituted by a resistor 5-2 and a capacitor 5-8 with a threshold value of the third inverter. For this reason, it was difficult to obtain a large delay time. If such large delay time is intended to be obtained by this delay circuit, a time constant of the circuit constituted by the resistor and the capacitor must be made large. However, if the time constant becomes large, an amplitude of a potential at the node NC becomes small as shown in FIG. 4A. For this reason, a change of a threshold value of the succeeding inverter due to the changes of the temperature and the threshold voltage and the like will change the waveform of the output signal, resulting in unstable delay time of the signal. Note that FIG. 4B shows a potential at the node ND.
According to the Miller-integrator type delay circuit shown in FIG. 7, the triangular waveform output from the second inverter 7-2 must not be distorted in order not to distort the output signal waveform. In order to secure the operation of the second inverter, an integrator constituted by the second inverter 7-2, the resistor 7-4 and the capacitor 7-5 must have a sufficiently large dynamic range.
For this reason, it is difficult to use this type of delay circuit as an equipment whose power supply voltage is 2.5 [V] or less such as a portable equipment, and particularly an equipment whose power supply voltage is 1.5 [V] or less.